Conference Paper RDF
pages:- Logical circuit gate sizing using MPSO guided by Logical Effort - an examination of the 12-stage ripple carry adder circuit
- Logical circuit gate sizing using MPSO guided by Logical Effort - An examination of the 4-stage half adder circuit
- Logical circuit gate sizing using MPSO guided by Logical Effort - An examination of the 8-stage full adder circuit
- Logical circuit gate sizing using PSO guided by Logical Effort
- Logical circuit gate sizing using PSO guided by Logical Effort - an examination of the 12-stage ripple carry adder circuit
- Logical Effort using a Novel Discrete Particle Swarm Optimization algorithm
- Logical effort using Particle Swarm Optimization algorithm — An examination on the 8-stage full adder circuit
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